New PDF release: Noise-Shaping All-Digital Phase-Locked Loops: Modeling,

By Francesco Brandonisio, Michael Peter Kennedy

ISBN-10: 3319036580

ISBN-13: 9783319036588

ISBN-10: 3319036599

ISBN-13: 9783319036595

This ebook offers a singular method of the research and layout of all-digital phase-locked loops (ADPLLs), expertise ordinary in instant conversation units. The authors offer an summary of ADPLL architectures, time-to-digital converters (TDCs) and noise shaping. lifelike examples illustrate the right way to examine and simulate section noise within the presence of sigma-delta modulation and time-to-digital conversion. Readers will achieve a deep figuring out of ADPLLs and the vital function performed by means of noise-shaping. a number ADPLL and TDC architectures are provided in unified demeanour. Analytical and simulation instruments are mentioned intimately. Matlab code is incorporated that may be reused to layout, simulate and examine the ADPLL architectures which are provided within the book.

• Discusses intimately a variety of all-digital phase-locked loops architectures;
• offers a unified framework within which to version time-to-digital converters for ADPLLs;
• Explains a method to foretell and simulate part noise in oscillators and ADPLLs;
• Describes a good method of version ADPLLS;
• comprises Matlab code to breed the examples within the book.

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Additional resources for Noise-Shaping All-Digital Phase-Locked Loops: Modeling, Simulation, Analysis and Design

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28 measures the fractional part of the phase of the reference oscillator on the edges of Re f R . The TDC in Fig. 28 is started and stopped on the edges of Ref and the next edges of the DCO, respectively. Hence, the normalization factor of the TDC output is the period of the reference oscillator. Different from a PFD-plusTDC based ADPLL, the normalization factor of the TDC in an accumulator-based ADPLL with retiming does not have to be changed over time because the TDC is 30 2 Phase Digitization in All-Digital PLLs Fig.

42 3 A Unifying Framework for TDC Architectures Fig. 4 Block diagram of a Delay-Line-based TDC implemented with D-Flip-Flops and Delay elements Fig. 5 Timing diagram of the transitions of the D-FlipFlops in a delay-line-based TDC The operation of a delay-line-based TDC can be related to that of a flash ADC that is described in Sect. 2 In fact, the transitions of the delay elements can be associated with a series of thresholds th(m), where th(m) is the sum of the delays of the first m delay elements of the delay line, as illustrated in Fig.

34 Fractional-N TDC-based ADPLL with an accumulator that sets the fractional part Nfrac of the division ratio ing in the literature. By contrast, an accumulator-based ADPLL which synthesizes fractional division ratios is obtained by introducing a fractional part in the digital word INC such that the accumulator in the accumulator-based ADPLL accumulates INC = INCint + INCfrac . A similar approach can be applied to a TDC-based ADPLL by introducing an accumulator that increases by INCint every time an edge of Ref occurs, as shown in Fig.

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Noise-Shaping All-Digital Phase-Locked Loops: Modeling, Simulation, Analysis and Design by Francesco Brandonisio, Michael Peter Kennedy

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