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By Douglas A. Pucknell

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N-well CMOS circuits are also superior to p-well because of the lower substrate bias effects on transistor threshold voltage and inherently lower parasitic capacitances associated with source and drain regions. 11. The first mask defines the n-well regions. This is followed by a low dose phosphorus implant driven in by a high temperature diffusion step to form the n-wells. The well depth is optimized to ensure against p-substrate top+ diffusion breakdown without compromising then-wellton+ mask separation.

Indeed, a problem of p-well and n-well CMOS processing is that parasitic bipolar transistors are inadvertantly formed as part of the outcome-Qf fabrication. The production of npn bipolar transistors with good performance characteristics can be achieved, for example, by extending the standard n-well CMOS processing to include further masks to add two additional layers-the n+ subcollector and p+ base layers. The npn transistor is formed in an n-well and the additional p+ base region is located in the well to form the p-base region of the transistor.

12 Basic VLS/ Design ) OBSERVATIONS This chapter has set the scene by introducing the basically simple MOS transistor structures and the relatively straightforward fabrication processes used in the manufacture of nMOS, CMOS and BiCMOS circuits. We have also attempted to emphasize the revolutionary spread of semiconductor technology which has, in the short space of 30 years, advanced to a point where we now see complex systems completely integrated onto a single chip. Although this text concentrates on digital circuits and systems, similar techniques can be .

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Basic VLSI Design by Douglas A. Pucknell


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